SPMT Technology Japanese







Tokyo Conference Center at Shinagawa

          Shinagawa, Tokyo (Japan)

                September 17, 2010

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AGENDA


09:30 to 10:00 -

Registration

10:00 to 10:05 -

Welcome and speaker introduction

10:05 to 10:45 -

Introduction to SPMT ™ (Serial Port Memory Technology)
Motivation, system requirements and SerialSwitch™ Technology

10:45 to 11:00 –

Break

11:00 to 11:30 -

Introduction to SPMT ™ (Serial Port Memory Technology) (cont’d)
Comparison to existing technologies and the migration path from parallel to serial memories

11:30 to 12:00 -

Q&A

12:00 to 13:00 –

Lunch Break

13:00 to 13:45 -

Cost Analysis
Pin savings, die area, board area, integration, test and test equipment, packaging

13:45 to 14:00 -

Q&A

14:00 to 14:45 -

System Architecture
Bandwidth factors, memory prefetch, interface frequency, lane width, density and memory controller

14:45 to 15:00 -

Q&A

15:00 to 15:15 –

Break

15:15 to 16:00 -

Signal Integrity
Memory specification, bit error rate, system compliance, error detection and correction

16:00 to 16:15 -

Q&A

16:15 to 17:00 -

The Business Case for Serial Port Memory Technology
Mobile, consumer, and embedded solutions; power and bandwidth advantages; the SPMT Consortium and market adoption