Tokyo Conference Center at Shinagawa
Shinagawa, Tokyo (Japan)
September 17, 2010
 | Jim Venable
President
SPMT LLC |
Jim Venable has more than 25 years experience in the semiconductor and IP industry, with extensive experience in engineering, marketing and business development. He has held senior management positions with Motorola, Mentor Graphics, Hitachi, Sharp and AMD, where he was responsible for product strategy and market development. Most recently, at Silicon Image, Venable was responsible for driving the company’s emerging advanced memory IP products into the mobile and consumer electronics market segments. He has appeared on numerous industry panels and spoken at many events, including Embedded Systems Conference, MemCon, and IP conferences worldwide. Venable received his degree in electrical engineering from Texas Tech University.
|
 | Alan Ruberg
Chief Architect
SPMT LLC |
Alan Ruberg is the systems architect for the SPMT's Consortium. He played an instrumental role in the development of three DRAM chips based on serial interface technology, and is the primary author of the SPMT Interface Specification.
Previously, Alan was at Sun Microsystems Laboratories working on embedded systems for ultra-thin desktop and multimedia appliances. His expertise spans video server and network architectures, operating systems and instruction set support for media applications, contributions to the Java Media Framework, as well as pioneering work in network video conferencing, collaboration, and presentation tools.
|
 | Roger Isaac
Sr. Manager Marketing & Business Development
SPMT LLC |
| Roger Isaac is the senior manager of marketing and business development for the SPMT™ Consortium. He has over 10 years of experience in the semiconductor industry, focusing on memory architectures and high-performance systems. Prior to joining SPMT, Roger was Senior Member of Technical Staff at Spansion where he played an instrumental role in engineering the next-generation interface for both volatile and non-volatile memories. He also worked at Advanced Micro Devices where he developed high-performance memory subsytems for AMD’s next-generation CPUs.
Roger has a Master of Science in computer engineering from North Carolina State University, a Bachelor of Science in computer engineering from Georgia Institute of Technology, and an MBA from the University of Texas at Austin. Roger serves as the Vice-Chairman of the JEDEC JC42.6 sub-committee for low power memories for mobile designs. He holds multiple patents and industry accolades including Chairman’s awards from JEDEC.
|