SPMT™ (Serial Port Memory Technology) with SerialSwitch™ technology
Today’s mobile device market must respond to growing demands for ever higher performance, lower power consumption, reduced pin count, and reduced costs. DRAMs based on parallel interface technologies are rapidly exhausting their ability to meet these new demands due to pin count constraints, as well as performance and power limitations. In order to meet future mobile requirements, a new type of memory is required that takes DRAM performance to a new level, while at the same time dramatically reducing pin count and power.
SPMT™ (Serial Port Memory Technology) is the industry’s first high-performance serial memory interface architecture standard for DRAM. The technology offers low power, high bandwidth, reduced pin count, and overall system cost reductions. Serial Port Memory Technology targets mobile and consumer electronics applications with high bandwidth requirements like HD video, 3D gaming, mobile projection, and more.
SerialPortMemory Technology introduces the SerialSwitch™ memory interface architecture that employs both a serial interface and a parallel interface. Developed by the SPMT Consortium, SerialSwitch technology offers the best of both worlds: the low start-up latency and low power consumption in low-bandwidth environments of a parallel interface combined with the ultra-high performance, low pin count, and low power in high-bandwidth environments of a serial interface.
SPMT-enabled memory with SerialSwitch technology can automatically switch to high-performance SPMT serial mode with bandwidths ranging from 1.6 GB/s in parallel mode to 6.4 GB/s in serial mode. SerialSwitch technology delivers four times the bandwidth pin-for-pin at half the power of existing memory solutions, and offers smooth, low cost migration from parallel to serial memories.
Key characteristics of SPMT-enabled memory with SerialSwitch Technology:
- Flexible bandwidth from 400MBytes up to 12.8GBytes per second with future scalability
- Best in class I/O power consumption in all bandwidth environments
- Pin savings of up to 75%, which simplifies design and reduces per-unit cost
- Addresses customer low power/latency requirements
- Low latency exit from power down states
- Low latency across all bandwidths
- Parallel DRAM mode hides PLL startup latency
- Plug-in replacement for LPDDR2
- Compatible with all LPDDR2 packages
- Integrates with existing memory cores
Download the SPMT whitepaper to read about market trends and challenges, the limitations of current parallel memory technology, and how SPMT-enabled memory can revolutionize the mobile device industry.